Low leakage local oscillator system

ABSTRACT

Local oscillator apparatus comprising communication signal terminals for a communication signal, especially in a receiver or a transmitter, and a controlled frequency oscillator for producing a local oscillator signal. The local oscillator also includes a reference frequency generator and a feedback loop for selecting and adjusting the frequency of the local oscillator signal relative to the frequency of said reference frequency signal. A first frequency divider divides the frequency of the local oscillator signal by a first division factor to produce a conversion signal, where the frequency of said conversion signal is at least approximately equal to the frequency of the communication signal, and conversion means responsive to the conversion signal converts between said communication signal and base-band signal. A second frequency divider divides the frequency of the local oscillator signal by a second division factor and is connected in the feedback loop, where the division factor is different to the second division factor and the ratios between said first and second division factors are fractional.

FIELD OF THE INVENTION

This invention relates to low leakage local oscillator apparatus and toa communications system including such apparatus. The invention isparticularly, but not exclusively, applicable to in communicationsapparatus in which the communications signal is combined with a signalderived from the local oscillator.

BACKGROUND OF THE INVENTION

Local oscillators are used in various electronic circuits to generate asignal to be combined with a communication signal. Such is the case, forexample, in direct-conversion receivers and transmitters, in which thecommunication signal is converted in a single step betweencommunications frequency and base-band frequency. In the case of a radioreceiver, a radio signal received may be directly down converted toIn-phase (I) and Quadrature-phase (Q) signals and, in the case of aradio transmitter, a radio signal to be transmitted may be directly upconverted from In-phase (I) and Quadrature-phase (Q) signals. Suchdirect-conversion receivers and transmitters enable a high degree ofintegration of the circuits, for example by avoiding the need forband-pass filters, as are required in heterodyne receivers andtransmitters.

It is important to minimise the effect of spurious signals also beingcombined with the communication signal, such spurious signals appearingas a consequence of ‘leakage’, the propagation of unwanted, parasiticsignals generated by the local oscillator and other circuits in thecommunications apparatus.

A direct-conversion receiver is described in U.S. Pat. No. 5,530,929,including a local oscillator that is connected to a first processingunit that multiplies the output frequency of the local oscillator by afactor M. The first processing unit is operatively connected to a secondprocessing unit in which the output signal of the first processing unitis divided by a factor N. M and N are both integer numbers and examplesare given with M=3 and N=2 and with M=2 and N=3. The output signal fromthe second processing unit is supplied to I and Q mixers where itperforms a homodyne conversion to base-band of the incoming RFcommunication signal, at least the second processing unit beingintegrated with the mixers to reduce propagation of spurious signals.

SUMMARY OF THE INVENTION

The present invention provides local oscillator apparatus, receiverapparatus and transmitter apparatus as claimed in the claims herebelow.

The invention is applicable to radio receivers and transmitters and alsoto other communication systems, such as cable communication systemsinvolving use of low leakage local oscillators.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block schematic diagram of a radio receiver not using thepresent invention,

FIG. 2 is a block schematic diagram of a radio receiver in accordancewith one embodiment of the invention,

FIG. 3 is a block schematic diagram of a radio transmitter not using thepresent invention,

FIG. 4 is a block schematic diagram of a radio transmitter in accordancewith another embodiment of the invention, and

FIG. 5 is a block schematic diagram of a radio receiver in accordancewith yet another embodiment of the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The communications apparatus shown in the drawings are direct (orpseudo-direct) conversion receivers (or transmitters) that immediatelydown convert (up convert) the received radio signal (the transmit radiosignal) to (from) a base-band signal thus completely eliminating anyintermediate frequency IF stage (as would be found in a heterodynereceiver or transmitter). However, prior art receivers of this kind havesuffered from the formation of a very large unwanted dc componentinterfering with the base-band signal. This dc component is formedlargely by leakage from the local oscillator being received (ortransmitted) at the receiver (at the transmitter) aerial together withthe wanted signal, and also by offsets of the amplifiers and mixers inthe receivers.

In order to overcome this problem, the frequency fVCO of the signalgenerated by the Voltage Controlled Oscillator (RF VCO) and mixed withthe communication signal is a multiple M of the communication radiofrequency. The multiple M is preferably an even number which simplifiesthe generation of I and Q components with a phase difference of 900 froma common signal and is preferably 4 times or 2 times, so as to limit thefrequency of the voltage controlled oscillator.

Referring to FIG. 1, the direct conversion receiver shown, which doesnot incorporate the present invention, comprises an integrated circuit100 having differential input terminals LNA_IN and LNA_INX for receivingthe RF communication signal at a frequency of fRF, differentialquadrature output terminals IRX, NIRX and QRX, NQRX for output of thebase-band communication signal after conversion, a phase-locked loop(PLL) feedback output terminal fLO_feedback and an input terminal VTUNEfor tuning voltage signal of the PLL.

The integrated circuit 100 includes a low noise amplifier whose inputsare connected to the differential input terminals LNA_IN and LNA_INX andwhose differential outputs are connected to the inputs of Q and I mixers102 and 103. The differential outputs of the mixers are connected to thedifferential quadrature output terminals IRX, NIRX and QRX, NQRX. Theintegrated circuit 100 also includes a voltage controlled oscillator 104whose RF frequency fVCO is tuned by the voltage appearing at the inputterminal VTUNE. The differential outputs of the voltage controlledoscillator 104 are connected to the inputs of an I/Q frequency dividercircuit 105 which generates quadrature signals ILO+, ILO− and QLO+, QLO−at a frequency FILO equal to fVCO/M, where M is an integer. The I/Qfrequency divider circuit 105 does not need to include phase shiftcomponents if the frequency division factor M is an even number.

The differential Q and I outputs of the I/Q frequency divider circuit105 are connected to the inputs of the respective mixers 102 and 103.The differential outputs of the voltage controlled oscillator 104 arealso connected to the inputs of a buffer amplifier 107, which produces asimple output signal, its output being connected to the feedback outputterminal fLO_feedback.

The above elements are all included in the integrated circuit 100.However the receiver also includes a feedback loop, external to theintegrated circuit 100. The feedback loop comprises a phase-lock loopcircuit 108 of the fractional-N kind capable of dividing a referencefrequency by a selected fractional number, that is to say a number thatmay be a non-integer. Output frequency step sizes that are fractions ofthe reference signal frequency are obtained while maintaining a highreference frequency and wide loop bandwidth. Suitable fractional-N phaselock loops may be found in U.S. Pat. Nos. 5,166,642 and 5,530,929(Hietala et al., assigned to the assignee of the present invention). Thefact that the phase-lock loop is on a separate substrate avoids directleakage to sensitive elements of the receiver such as the low noiseamplifiers.

The phase-lock loop circuit 108 has one input connected to the feedbackoutput terminal fLO_feedback and an output connected to a low passfilter 109. A crystal controlled oscillator 110 generates a frequencyreference signal at a fixed reference frequency fxtal, its output beingconnected to another input of the phase-lock loop circuit 108. A digitaladder circuit 111 receives a digital frequency correction word AFC andadds it to a digital RF channel number selection signal ARFCN. Theoutput of the adder circuit is connected to a digital fractionalisationand noise-shaping circuit 112 to select the internal fractional numberof the phase lock loop that defines the ratio of the desired frequencyto the reference frequency fxtal supplied by the crystal controlledoscillator 110 to its input; the output of the digital fractionalisationand noise-shaping circuit 112 is connected to yet another input of thephase-lock loop circuit 108.

In operation of the receiver shown in FIG. 1, the phase-lock loopcircuit 108 compares the phase of the signal at the feedback outputterminal fLO_feedback, which is at the actual frequency fVCO of thevoltage controlled oscillator 104, with the desired frequency obtainedby dividing the reference frequency fxtal by the selected internalfractional number of the phase-lock loop, with fine tuning capability.The voltage produced by the result of the comparison, filtered by thefilter 109, controls the frequency of the voltage controlled oscillator104 to the desired frequency.

In the receiver of FIG. 1, the frequency of the signal at the feedbackterminal fLO_feedback=fvCO=fRF/M (where preferably M=4 or 2).

The phase-lock loop is external to the integrated circuit 100 andgenerates only low levels of spurious signals, which can be keptseparate to a large extent from the communication signal. However thelocal oscillator feedback signal is routed from one integrated circuitto another, at the feedback output terminal fLO_feedback and some localoscillator leakage can still propagate to the input terminals LNA_IN andLNA_INX due to limited isolation that would be present within the RFintegrated circuit 100 which at the current state of the art is measuredto −50 dB in the 2 Ghz frequency range.

So the input of the low noise amplifier 101 will see a leakage signal ata frequency equal to fVCO and then this leakage signal (LO leakage) willmix also with the frequencies of the outputs of the divider M 105 whichare all harmonics of fVCO/M.

The Mth harmonics of fVCO/M at the divider outputs will mix with thefLO_feedback resulting in a low DC offset (even if this Mth harmonic issmall due to differential strucutre), that is measured in currenttechnology to −95 dbm (reference IEEE 2001. “WBCDMA Zero-IF Front-Endfor UMTS in a 75 Ghz Sige BiCMOS Technology”, authors: Harald Pretl, . .. ).

So fLO_feedback(LO leakage)=fVCO=fRF*M(LO leakage harmonically relatedto the input wanted frequency).FILO=x*fVCO/M=x*fRF

So for x=M, this results in a DC offset output.

Also, fLO_feedback (LO leakage) can also generate sub-harmonic signalsdue to the shape of the signal LO_feedback which falls to the input RFfrequency.

Thus the amount of leakage frequency located at the same frequency asthe input received signal is not completely eliminated and can bemeasured at a level higher than the lowest wanted signal to be received.

Referring to FIG. 2, this shows a block diagram of a direct conversionreceiver in accordance with the present invention; it will beappreciated that the invention is also applicable to a pseudo directconversion receiver. Similar elements in FIG. 2 bear the same referencenumbers as the corresponding elements of FIG. 1 but increased by 100,the integrated circuit 100 of FIG. 1 becoming the integrated circuit 200of FIG. 2, and so on.

In addition to the elements of the receiver shown in FIG. 1, thereceiver of FIG. 2 also includes a fixed divider 206 whose differentialinputs are connected to the outputs of the I/Q voltage controlledoscillator 204 and whose differential outputs are connected to theinputs of the buffer amplifier 207, so that the divider 206 is connectedin series in the feedback loop and divides the frequency fVCO of thevoltage controlled oscillator 204 by a factor N.

The factor N is chosen so that the frequency of the LO feedback signalappearing at the feedback output terminal fLO_feedback is notharmonically related to the input wanted frequency fRF.fLO _(—feedback)(LO leakage)=fVCO/NfRF(input wanted frequency)=fVCO/MfLO_feedback=M/N*fRF

N is chosen to be different to M and the ratios M/N and N/M are chosento be fractional (that is to say non-integers). Preferably M is an evennumber, if only to facilitate the generation of quadrature signals, asmentioned above.

If M is an even number, N is preferably an odd number greater than 1 ora multiple of an odd number greater than 1. If M=2*p, then N ispreferably chosen equal to 2*p+1 or 2*p−1 such thatFLO _(—feedback=)2*p/(2*p+1)*fRF or 2*p/(2*p−1)*fRF

This relationship ensures that the LO leakage is not harmonicallyrelated to the input wanted frequency fRF, thus further reducing theeffect of the LO leakage on the wanted signal (i.e the generated DCoffset at the mixer outputs (202 and 203) and it is possible to reducethe leakage to a level lower than −120 dbm without any shielding.

In preferred but non-limitative examples of this embodiment of theinvention,

-   -   p=1, M=2, N=3 (N=1 is not selected on this case only since this        make the LO-feedback harmonically related.) or    -   p=2, M=4, N=5 or N=3 or    -   p=4, M=8, N=7 or N=9.        The GSM (Global System for Mobile communications) standards or        WBCDMA (Wide Band Code Division Multiple Access) standards of        the European Telecommunications Standards Institute (ETSI) have        channel steps of 200 khz. Since the fLO_feedback=M/N*fRF, in the        case of the present embodiments of this invention, this results        in a requirement for frequency steps of M/N*200 khz to be done        by the phase locked loop, which is a fractional number of 200        khz. The use of the fractional-N phase-lock loop in conjunction        with the frequency divider 206 dividing by N enables this to be        achieved with extremely low leakage levels.

Note also that the use of a divider by N rather than a multiplier (as inU.S. Pat. No. 5,530,929 referred to above) creates substantially lessphase noise since multipliers multiply the phase noise of the voltagecontrolled oscillator.

Referring to FIG. 3, this shows a block diagram of a direct conversiontransmitter which is not in accordance with the present invention.Similar elements in FIG. 3 bear the same reference numbers as thecorresponding elements of FIG. 1 but increased by 200, the integratedcircuit 100 of FIG. 1 becoming the integrated circuit 300 of FIG. 3, andso on.

An output radio frequency signal to be transmitted at frequency fRF isprocessed by a voltage gain attenuator (VGA) 301 driven from aquadrature pair of mixers 302 and 303. The quadrature pair of mixers 302and 303 have as inputs the base-band signal and the conversion signalsILO+,ILO− and QLO+,QLO− derived from the integrated RF VCO 304 frequencyfVCO by a frequency divider 305 dividing by M. M is again preferablyequal to 4 (or 2) to facilitate deriving the quadrature oscillatorinjection signals ILO+,ILO− ana QLO+,QLO.

A phase-lock loop PLL 308 that is of the fractional-N kind is used tocontrol the integrated voltage controlled oscillator 304, by comparingthe LO feedback signal derived from the buffer output stage 307 to theradio reference crystal clock 310.

Since the phase-lock loop 308 is fractional with fine tuning capabilityand has internally the pre-scaler divider stage, the digital correctionfrequency word AFC is added to the selected channel to be transmittedARFCN and used as reference word to the digital fractionalisation block312 to derive control words for the fractional N phase-lock loop 308.

In the transmitter circuit shown in FIG. 3, the frequencyfLO_feedback=fvCO=fRF/M where M=4 or 2.

Spurious signals originating from the terminals fLO_Feedback willradiate to the VGA output (301) due to limited isolation that would bepresent within the RF IC (300) which at the current technology art ismeasured to −50 dB at 2 Ghz frequency range.

So the frequency fLO_feedback(LO leakage)=fVCO=fRF*M (LO leakageharmonically related to the output wanted frequency).

Also, the frequency fLO_feedback (LO leakage) can also generatesub-harmonic signals due to the shape of LO_feedback signal which fallsto the output RF frequency. This results in a spurious signal falling atthe same frequency as the wanted transmit frequency which will distortthe transmit signal and increase the Error Vector Modulation (EVM) byoffsetting the modulation from an ideal modulation, especially when thewanted transmit signal level is reduced due to power controlrequirements done on the VGA (301), whereas the LO leakage level is notreduced, the LO leakage level thus increasing relative to the wantedtransmit frequency level.

FIG. 4 shows a block diagram of a direct conversion transmitter inaccordance with the present invention. Similar elements in FIG. 4 bearthe same reference numbers as the corresponding elements of FIG. 3 butincreased by 100, the integrated circuit 300 of FIG. 3 becoming theintegrated circuit 400 of FIG. 4, and so on.

In addition to the elements of the transmitter shown in FIG. 3, thetransmitter of FIG. 4 also includes a fixed divider 406 whosedifferential inputs are connected to the outputs of the I/Q voltagecontrolled oscillator 404 and whose differential outputs are connectedto the inputs of the buffer amplifier 407, so that the divider 406 isconnected in series in the feedback loop and divides the frequency fVCOof the voltage controlled oscillator 404 by a factor N.

The factor N is chosen so that the frequency of the LO feedback signalappearing at the feedback output terminal fLO_feedback is notharmonically related to the input wanted frequency fRF.fLO_feedback(LO leakage)=fVCO/NfRF(input wanted frequency)=fVCO/MfLO_feedback=M/N*fRF

N is chosen to be different to M and the ratios MIN and N/M are chosento be fractional (that is to say non-integers). Preferably M is an evennumber, if only to facilitate the generation of quadrature signals, asmentioned above.

If M is an even number, N is preferably an odd number greater than 1 ora multiple of an odd number greater than 1. If M=2*p, then N ispreferably chosen equal to 2*p+1 or 2*p−1 such thatFLO_feedback=2*p/(2*p+1)* fRF or 2*p/(2*p−1)*fRF

This relationship ensures that the LO leakage is not harmonicallyrelated to the output transmitter frequency fRF, thus further reducingthe effect of the LO leakage on the transmitted communication signal.

In preferred but non-limitative examples of this embodiment of theinvention,

-   -   p=1, M=2, N=3 (N=1 is not selected on this case only since this        make the LO-feedback harmonically related.) or    -   p=2, M=4, N=5 or N=3 or    -   p=4, M=8, N=7 or N=9.

Since the fLO_feedback=M/N*fRF, for a channel step of 200 khz like inGSM or WBCDMA, this results in M/N*200 khz frequency step to be done bythe phase locked loop, which is a fractional number of 200 khz. The useof the fractional-N phase-lock loop in conjunction with the frequencydivider 206 dividing by N enables this to be achieved with extremely lowleakage levels.

In the case of a multi-standard transmitter/receiver, the selection ofN=2*p−1 or 2*p+1 depends on the presence of several radios within theterminal unit and the selection of 2p−1 or 2p+1 is done such a way thatno frequency is created that could block a received signal.

For example, in the case of a terminal including a WBCDMA transmitterand a GPS receiver (GPS is the Global Positioning System managed by theInteragency GPS Executive Board (IGEB) established by the USAgovernment), it is preferable to select N=3 rather N=5 to avoid creatingan LO feedback frequency that falls at almost the same receivedfrequency of GPS (1575 Mhz).

fTX 1920-1980 Mhz fRX 2110-2170 Mhz WBCDMA IMT2000 fTX (WBCDMA) fLO(WBCDMA) 2*fLO 3*fLO 4*fLO M (VCO mixer divider) 2 1920 768 1536 23043072 N (VCO LO divider) 5 1930 772 1544 2316 3088 1940 776 1552 23283104 1950 780 1560 2340 3120 1960 784 1568 2352 3136 1970 788 1576 23643152 1980 792 1584 2376 3168 *Spurs Blocking for GPS

fTX 1920-1980 Mhz fRX 2110-2170 Mhz WBCDMA IMT2000 fTX (WBCDMA) fLO(WBCDMA) 2*fLO 3*fLO 4*fLO M (VCO mixer divider) 2 1920 1280 2560 38405120 N (VCO LO divider) 3 1930 1286, 667 2573, 333 3860 5146, 667 19401293, 333 2586, 667 3880 5173, 333 1950 1300 2600 3900 5200 1960 1306,667 2613, 333 3920 5226, 667 1970 1313, 333 2626, 667 3940 5253, 3331980 1320 2640 3960 5280

It will be understood that the phase-lock loops are separate from theintegrated circuit that includes the input or output terminals LNA_IN,LNA_INX; RF_OUT, RF_OUTN, the voltage controlled oscillators 204; 404,the frequency dividers 205; 405, the mixers 202, 203; 402, 403 and thelow noise amplifiers or voltage gain attenuators 201; 401 enablescircuits that would be liable to propagate spurious signals within theintegrated circuit, such as the digital noise shaping circuits 212; 412to be used without spurious signals propagating to the low level lownoise circuits like low noise amplifiers (LNA) and down-converted mixers(or up-converted mixers and voltage gain attenuators (VGA) fortransmitters).

As the fractional-N phase-lock loops are external to the RF Integratedcircuits, the local oscillator feedback signal is routed from one IC toanother IC. With circuits of the kind shown in FIG. 1 or FIG. 3, whichare not in accordance with the present invention, the residual localoscillator leakage would still be sufficiently high to requireshielding, which is inconvenient and costly and not always sufficientlyeffective. The present invention enables satisfactorily low leakagelevels to be achieved without the need for shielding, especially in thistype of direct conversion receiver and transmitter.

FIG. 5 shows an advantageous variant of the receiver shown in FIG. 5.Similar elements in FIG. 5 bear the same reference numbers as thecorresponding elements of FIG. 2.

In addition to the elements of the receiver shown in FIG. 2, thereceiver of FIG. 5 also includes a transformer 213 comprising a firstcoil connected to the outputs of the low noise amplifier 201 and asecond coil, inductively coupled to the first coil and connected to theinputs of the mixers 202 and 203. The inductances and internalcapacitances of the coils of the transformer form a circuit tuned to thefrequency fRF of the communication signal so as to form a so-called‘balun’.

In operation, the transformer 213 performs an impedance transformationbetween the low noise amplifier 201 and the mixers 202 and 203. Itadditionally acts as a band-pass filter to filter out of band blockers(or unwanted signals). In particular, the transformer will filter the LOleakage harmonics, for example the 5^(th) harmonics of the residual LOleakage. With the frequency fVCO at 4 Ghz, the frequencyfLO_feedback=800 Mhz, and the frequency of the 5^(th) harmonic=5*800=4Ghz. The wanted signal is at 1 Ghz, so the 5^(th) harmonics will be outof the pass-band of the transformer and will be attenuated before mixingcould result in low frequency (DC) offsets.

While the above embodiments of the invention have been described withreference to receivers or transmitters, it will be understood thatfrequently a terminal will include both a receiver and a transmitter,which may be arranged to have elements in common. Such will normally bethe case for a portable telephone handset, for example.

1. Local oscillator apparatus comprising: communication signal terminalsfor a communication signal, controlled frequency oscillator means forproducing a local oscillator signal, reference frequency means forproducing a reference frequency signal, feedback loop means forselecting and adjusting the frequency of said local oscillator signalrelative to the frequency of said reference frequency signal, saidfeedback loop means including fractional-number dividing means fordividing said reference frequency by a programmable fractional numberand supplying a feedback signal to control the frequency of saidoscillator means, first frequency divider means for dividing thefrequency of said local oscillator signal by a first division factor toproduce a conversion signal, where the frequency of said conversionsignal is at least approximately equal to the frequency of saidcommunication signal, and conversion means responsive to said conversionsignal for converting between said communication signal and a base-bandsignal, characterised in that second frequency divider means fordividing the frequency of said local oscillator signal by a seconddivision factor is connected in said feedback loop means between saidcontrolled frequency oscillator means and said fractional-numberdividing means so that said fractional-number dividing means isresponsive to the relative values of said reference frequency divided bysaid programmable fractional number and said frequency of said localoscillator signal divided by said second division factor, where thefirst division factor is different to the second division factor and theratios between said first and second division factors are fractional. 2.Local oscillator apparatus as claimed in claim 1, characterised in thatsaid first and second division factors are integers greater than
 1. 3.Local oscillator apparatus as claimed in claim 2, characterised in thatsaid first division factor is an even number.
 4. Local oscillatorapparatus as claimed in claim 3, characterised in that said seconddivision factor comprises a factor that is an odd number.
 5. Localoscillator apparatus as claimed in claim 3, characterised in that saidsecond division factor is an odd number.
 6. Local oscillator apparatusas claimed in claim 2, characterised in that said second division factorcomprises a factor that differs by 1 from a factor of said firstdivision factor.
 7. Local oscillator apparatus as claimed in claim 2,characterised in that said second division factor differs by 1 from saidfirst division factor.
 8. Local oscillator apparatus as claimed in claim1, characterised in that said communication signal terminals, saidcontrolled frequency oscillator means, said first frequency dividermeans and said conversion means are included in an integrated circuitand said feedback loop means are separate from said integrated circuit.9. Local oscillator apparatus as claimed in claim 1, characterised inthat said feedback loop means comprises a fractional-number frequencysynthesizer arranged to divide said reference frequency in steps thatare a multiple of the ratio of said first division factor divided bysaid second division factor, whereby to change said frequency of saidconversion signal in steps equal to the channel spacing of thecommunication signal.
 10. Receiver apparatus comprising local oscillatorapparatus as claimed in claim 1, characterised in that saidcommunication signal is received at said communication signal terminals,said conversion means being adapted to combine said communication signalwith said conversion signal to produce said base-band signal. 11.Receiver apparatus as claimed in claim 10, characterised in that a lownoise amplifier means is connected to said communication signalterminals to receive said communication signal and a transformer isconnected between low noise amplifier means and said conversion means,said transformer presenting inductances and internal capacitances tosaid communication signal such as to form a band-pass filter tuned tothe frequency of the communication signal.
 12. Transmitter apparatuscomprising local oscillator apparatus as claimed in claim 1,characterised in that said communication signal is output at saidcommunication signal terminals, said conversion means being adapted tocombine said base-band signal with said conversion signal to producesaid communication signal.
 13. Terminal apparatus comprising transmitterapparatus as claimed in claim 12, characterised in that said terminalapparatus also includes receiver apparatus capable of receiving signalsin accordance with GPS standards, said transmitter apparatus beingcapable of transmitting a signal in accordance with WBCDMA standards andsaid first division factor being equal to 3.